1. Field of the Invention
This invention describes the design and layout of a basic core cell of gate array ASIC device. It relates to the technique of arranging the complimentary metal oxide semiconductor (here after referred to as CMOS) structures such as source / drain diffusion regions, gate oxide regions, contact holes, polysilicon, and metal electrodes. In particular it relates to the significant increase in circuit density, performance and decrease in circuit delays and power dissipation, this core cell offers over the prior art of gate array core cells used in ASIC devices. In addition to the CMOS process, this core cell design is equally applicable to gate array devices in the Silicon on Insulator (SOI) and BI-CMOS technologies. The gate array core cell design is independent of process design dimensions.
2. Brief Description of Prior Developments
A VLSI ASIC device requires large number of transistors, exceeding 20 million in some of the sub-micron ASICs on a single chip. A gate array master slice chip is illustrated in FIG. 12. It consists of an array of identical core cells occupying a major portion of the chip in the center and one row of primary input output buffer cells along the periphery of the chip. The core cell consists of predefined number of PMOS and NMOS transistors and the layout arrangement of these transistors. Formation of PMOS and NMOS transistors is a well-known prior art. Each transistor has a source and a drain diffusion region (here after referred to as xe2x80x9cS/Dxe2x80x9d) separated by the transistor channel. The channel is covered by thin oxide and the thin oxide is covered by polysilicon gate electrode. The function of S/D regions is interchangeable. Also in many layouts, two transistors may have a common source or drain region.
A gate array masterslice does not contain any predefined functional interconnections of the transistors. The masterslice wafers are only processed up to the formation of the self aligned polysilicon gate electrodes, in some cases as in this invention, polysilicon wire structures over thick oxide, and S/D regions. Many different ASIC components can be fabricated using the same gate array masterslice wafers. It is only during the process of each unique ASIC component that the transistors in the core cells and input/output buffer cells are interconnected to form various logic functions such as inverters, NANDs, NORs, ADDERS, LATCHES, receiver buffers, driver buffers, etc. Simultaneously the interconnections between the logic functions are formed to complete the ASIC component fabrications.
As the gate array masterslice is common to many unique gate array ASIC components, one mask-set is needed to process wafers up to the S/D formation steps. These process steps are also known as front end of the line (FEOL) steps. A large number of wafers are processed through the FEOL process and are kept in stock. Individual gate array ASIC components use master slice wafers from the stock thereby eliminating the FEOL processing time and cost of unique FEOL masks, as is the case for standard cell ASIC components. Each gate array ASIC requires a unique metal interconnection mask set also known as the back end of the line (BEOL) mask set.
The important characteristics of an ASIC component such as circuit density, performance, and power dissipation are directly dependent on the design of the core cell. It will be explained in details that the core cell presented in this invention offers significant improvements in the above mentioned characteristics over the gate array core cell designs in the prior art.
There are several types of gate array core cells in the prior art. The simplest forms are shown in FIG. 1A and FIG. 1B, where PMOS and NMOS transistors are arranged in continuous rows. These transistors are interconnected to form digital logic functions. In this configuration a large number of transistors are used just to isolate one circuit output from another circuit output, reducing the ASIC circuit density significantly. Further more all transistors need to be interconnected at metal level or levels only, taking many interconnecting wiring tracks, specifically if the function has cross coupling feedback loops such as in the Flip Flop circuits. This increases the core cell area, parasitic capacitance, circuit delays, and power dissipation in the ASIC. Another type of gate array core cell in the prior (layout not shown) art consists of a large number of transistors. Some of these transistors are used as pass transistors, some transistors are used for memory functions, and others form the logic functions. In ASICs designed with such core cells, a large percentage of transistors remain unused, thereby offering low circuit density at the ASIC chip level.
The present invention provides an optimum architecture of a gate array core cell. It can be used for efficient design of combinatorial logic cells such as NANDs, NORs, XORs, MUXs, data storage logic cells such as DFF, Flip Flops, and compiler based memory functions such as ROMs, SRAMs, dual port RAMs, and shift registers. The present invention essentially provides the means to design gate array ASICs with comparable circuit density, performance, and power dissipation to the standard cell ASICs while reducing the mask cost and ASIC component fabrication time to about half of the standard cell ASICs. The core cells include the following elements: (1) three P+ diffusion elements within one N-Well region. Each of these P+ diffusion regions contains two PMOS transistors. The N-Well region also includes a N+ diffusion region to connect the N-Well to the power supply (hereafter as VDD); (2) three N+ diffusion regions each of these N+ diffusion regions contain two NMOS transistors; (3) three N+ diffusion ESD diodes. All six PMOS transistors have the same width and length dimensions and similarly all six NMOS transistors are identical in width and length dimensions. Middle two PMOS transistor gate electrodes are connected to the middle two NMOS transistors in a cross coupled manner using polysilicon or local interconnect wires over a thick oxide region. The core cell also includes two polysilicon or local interconnect embedded wires. These wires when not used are shorted to the VDD and the GND buses. The usefulness of the predefined wiring of two of the PMOS transistors to two of the NMOS transistors and of the polysilicon embedded wires will become apparent in the detailed description of the invention. The core cell architecture has the defined location for the VDD and GND buses at metal level. It also has the defined location for the interconnecting wires to form the personality of the logic cell as well as for interconnections from logic cell to logic cell, in other words doing the interconnections for the complete ASIC function in the BEOL processing steps.
The core cell structures, S/D diffusion regions, transistor gate electrodes, polysilicon or local interconnect wires, N-Well to VDD diffusion region and the ESD diode diffusion regions are designed to accommodate contact holes for interconnections to the metal wires. Most of the wiring track locations at metal M1 are taken to form the personality of the basic logic cells leaving some metal M1 wiring tracks for logic cell to logic cell (global) interconnections. Metal M2 and metal M3 wires are used for global connections. Gate array compiled memory functions will also use some of the M2 wiring locations.
Circuit density of the gate array ASIC can be further improved using additional metal layers M4, M5 etc for global interconnections. BEOL processing steps are well known in the prior art of fabricating semiconductor components. These wafer fabrication steps include the formation of contacts to the diffusion regions and polysilicon regions deposition of metal layers separated by insulator layers, and connections between metal layers. The unique features and advantages of this invention over the prior art will be explained in the detailed description. Several commonly used logic circuits and their graphical layouts will be also described.